1. Field of the Invention
The present invention relates to non-volatile semiconductor memory elements, methods of manufacturing the non-volatile semiconductor elements, and semiconductor integrated circuit devices that include the non-volatile semiconductor memory elements.
2. Related Art
In a conventional non-volatile semiconductor memory device, the potentials of the control gate electrode and the source/drain regions are controlled, so that charge injection or charge emission is caused in the charge accumulating layer provided between the channel and the control gate electrode. By doing so, the amount of charges stored in the charge accumulating layer is adjusted so as to change the threshold voltage (the control gate voltage with which the region between the source and the drain of the element is switched between an ON state (a conduction state) and an OFF state (a non-conduction state)). In this manner, information is recorded in each memory element. In such a conventional non-volatile semiconductor memory device, one-bit information is recorded in each memory element by switching the threshold voltage between two values. Therefore, to increase the degree of integration, information of more than one bit needs to be recorded in each memory element. There has been known a type of non-volatile semiconductor memory device that includes memory elements each having charge accumulating layers on both sides of the channel and control gate electrodes over and below the channel, so as to store multivalue information of more than one bit. Each of such memory elements is equivalent to a structure having two conventional memory elements connected in parallel (see Japanese Patent Publication No. 3046376 and IP-A 10-125810 (KOKAI), for example).
When memory device that is equivalent to structure having two conventional memory elements connected in parallel is employed, the potentials of the two control gate electrodes of each memory element are controlled independently of each other, so that the amounts of charges in the two charge accumulating layers can be controlled independently of each other. Accordingly, information of more than one bit can be stored in each memory element. Further, there has been a method of achieving two or more different threshold voltages by fine-adjusting the amounts of charges stored in the charge accumulating layers.
In the non-volatiles semiconductor memory device that includes memory elements equivalent to structures each having two memory elements connected in parallel to each other so as to increase the degree of integration, however, two control gate electrodes are provided for each one memory element, which causes the problem that the wirings become more complicated than in a general non-volatile semiconductor memory device having one control gate electrode for each one memory element.
Also, by the method of achieving two or more different threshold voltages by fine-adjusting the amount of charges in each of the charge accumulating layers, the variation in the threshold voltage (hereinafter represented by “ΔVTH”) needs to be sufficiently small. The reason for this is as follows. In a case where 2-bit information is to be stored in each memory element, for example, it is necessary to adjust the threshold voltage to four different values. Even if the lowest threshold voltage has a negative value and the highest threshold voltage is higher than the power supply voltage (hereinafter represented by “VDD”), the other two threshold voltages need to fall between zero and VDD. Accordingly, it is necessary to satisfy the relation, VDD>2×ΔVTH. More specifically, where a verify function is not to be provided, ΔVTH is 2.3 V (as suggested by Masayuki Ichige et al., in “A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND Flash EEPROMs” in Technical Digest of 2003 Symposium on VLSI Technology, pp. 89-90), and if a verify function is to be provided, ΔVTH is 0.5 V (as suggested by Osama Khouri et al., in “Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories,” in Analog Integrated Circuits and Signal Processing, vol. 34 (2003), pp. 119-131). Accordingly, even where a verify function is to be provided, VDD cannot be made lower than 0.5 V×2=1 V. This greatly hinders a decrease in the power supply voltage that is required for reducing power consumption.